1. general description the 74ahc3gu04-q100 is a high-speed si-gat e cmos device. this device provides three inverter gates with unbuffered outputs. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? symmetrical output impedance ? high noise immunity ? low power dissipation ? balanced propagation delays ? multiple package options ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74ahc3gu04-q100 triple unbuffered inverter rev. 1 ? 18 november 2013 product data sheet table 1. ordering information type number package temperature range name description version 74AHC3GU04DP-Q100 ? 40 ? c to +125 ? c tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 74ahc3gu04dc-q100 ? 40 ? c to +125 ? c vssop8 plastic very thin sh rink small out line package; 8 leads; body width 2.3 mm sot765-1
74ahc3gu04_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 18 november 2013 2 of 15 nxp semiconductors 74ahc3gu04-q100 triple unbuffered inverter 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning table 2. marking codes type number marking code [1] 74AHC3GU04DP-Q100 au4 74ahc3gu04dc-q100 au4 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) mna720 1a 1y 17 2a 2y 35 3a 3y 62 7 1 1 1 5 3 mna721 1 2 6 mna045 ay fig 4. pin configuration sot505-2 (tssop8) and sot765-1 (vssop8) $ + & |